Method of forming a non-volatile electron storage memory and the resulting device

ABSTRACT

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

FIELD OF INVENTION

[0001] This invention relates to integrated circuit memory devices, and,more particularly, to a method and device for providing high-density,high-storage capacity, low-power, non-volatile memory devices.

BACKGROUND OF THE INVENTION

[0002] Non-volatile memory devices which store electrons innano-crystals instead of floating gates, are presently of greatinterest, due to potential advantages in memory cell size and powerdissipation, compared to memory technologies currently in use. The useof nano-crystals for electron storage will provide greater reliabilityand low-voltage operation. Research in this area is reported in thearticle “Volatile and Non-Volatile Memories in Silicon with Nano-CrystalStorage” by Tiwasi et al., IEEE, IEDM, 1995, pgs. 521-524, thedisclosure of which is incorporated herein by reference.

[0003]FIG. 1 is a sectional view illustrating a floating-gate n-channelMOS electron memory device. In the figure, reference numeral 1 denotes asilicon (Si) substrate, reference numeral 2 a tunnel gate oxide layer,reference numeral 4 a control gate oxide layer, reference numeral 5 acontrol gate electrode, reference numeral 6 a source region, referencenumeral 7 a drain region, reference numeral 8 an inversion layer, andreference numeral 3 silicon nano-crystals. This device is characterizedin that silicon nano-crystals 3 with a dimension, for example, of lessthan about 5 nm are provided between a tunnel oxide of 1.5 nm (or less)and control oxide of 7 nm or less. If alternate high dielectric constantdielectrics are employed, the physical film thickness can be greater, asthe “effective” thickness will be less due to the higher dielectricconstant of the dielectric material. A high dielectric constantdielectric is one which has a dielectric constant greater than silicondioxide.

[0004] During programming of the device, electrons contained in theinversion layer 8 tunnel into the silicon nano-crystals 3 on the tunneloxide layer 2 when the gate is forward biased with respect to the sourceand drain. The resulting stored charge in the silicon nano-crystals 3effectively shifts the threshold voltage of the device to a morepositive potential as the control gate now has to overcome the effectsof this change. The gate can also be programmed by a hot electrontechnique typically used in flash memory. The state of electrons in thesilicon nano-crystals 3 can be sensed by sensing a change in the currentflowing through the inversion layer 8 with respect to the gate voltage.

[0005]FIGS. 2A, 2B and 2C are views illustrating changes in theconduction band of the above-described device. When a positive voltagehas been applied to the gate with respect to the source and drainregions, an electron is transmitted and accumulated into the siliconnano-crystals 3 from the inversion layer 8 via the tunnel oxide layer 2,as is shown in FIG. 2A (“Write” state). Even if the application of thevoltage to the gate electrode 5 is removed, the electron is retained inthe silicon nano-crystals 3, as is shown in FIG. 2B (“Store” state). Thestored electron increases the threshold voltage of the transistor as itscreens the control gate voltage. On the other hand, when a negativevoltage has been applied to the gate with respect to the source anddrain regions, the electron accumulated in the silicon nano-crystals isdischarged to the substrate side via the tunnel oxide layer 2, as isshown in FIG. 2C. In this state, the threshold voltage returns to itsoriginal value (“Erase” state).

[0006] As described above, an electron can be transmitted into, retainedin, and discharged from the silicon nano-crystals 3, and the thresholdvoltage of the device varies depending upon whether or not electrons areaccumulated in the silicon nano-crystals 3. Hence, this device can beused as a memory device.

[0007] In the conventional floating-gate device using the storedelectron phenomenon, a low dielectric constant dielectric, such as SiO₂is used as a gate oxide layer. The SiO₂ gate oxide has a dielectricconstant of 3.9 which does not allow scaling and also does not permitlow voltage operation. Also, depending on what control gate oxide isused and subsequent processing steps used, the silicon nano-crystalscould oxidize, which would impede or destroy memory device operation.For example, if a high constant (high-K) dielectric, such as Ta₂0₅, isused as the control gate oxide to scale the gate threshold voltage forlow voltage application, formation of the Ta₂0₅ control gate oxide couldoxidize the silicon nano-crystals destroying the memory cell. Thepresent invention enables integration of high constant dielectrics,which in turn allows for reduction of operating voltages.

SUMMARY OF THE INVENTION

[0008] The invention provides a method of forming a semiconductor deviceand the resulting device which mitigates the foregoing problems. Thedevice comprises a gate structure having a first gate insulating layerformed over a semiconductor substrate and a electron trapping layercontaining a noble metal formed over the first gate insulating layer.Preferably, the noble metal is formed of platinum, rhodium, or rutheniumwhich enables self-forming nano-crystals. The self-forming nano-crystalseliminate the need for costly mask steps to form the nano-crystals.Further, the gate structure includes a second gate insulating layerformed over the electron trapping layer. In a preferred embodiment ofthe invention, the first gate oxide is preferably SiO₂ (silicondioxide), but a high dielectric constant advanced dielectric, such asTa₂O₅ (tantalum oxide), BaSrTiO₃ (barium strontium titanate), HfO₂(hafnium oxide), or ZrO₂ (zirconium oxide) can also be used. The gatestructure further includes a gate electrode formed on the second gateinsulating layer. Source and drain regions are provided in surfaceportions of the semiconductor substrate with the gate structure betweenthem.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above advantages and features of the invention as well asothers will be more clearly understood from the following detaileddescription which is provided in connection with the accompanyingdrawings.

[0010]FIG. 1 is a sectional view illustrating the structure of aconventional floating-gate device using the single electron effect;

[0011] FIGS. 2A-2C are views illustrating changes in the conduction bandof the device of FIG. 1;

[0012]FIG. 3 is a sectional view illustrating the structure of asemiconductor device at a processing step in accordance with theinvention;

[0013]FIG. 4 shows the device of FIG. 3 at a fabrication step subsequentto that shown in FIG. 3;

[0014]FIG. 5 shows the device of FIG. 3 at a fabrication step subsequentto that shown in FIG. 4;

[0015]FIG. 6 shows the device of FIG. 3 at a fabrication step subsequentto that shown in FIG. 5;

[0016]FIG. 7 shows the device of FIG. 3 at a fabrication step subsequentto that shown in FIG. 6; and

[0017]FIG. 8 shows a processor system having one or more memory devicesthat contains a computer electron storage device according to theinvention as shown in FIG. 7 and in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018] In the following detailed description, reference is made tovarious exemplary embodiments of the invention. These embodiments aredescribed with sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be employed, and that structural and electrical changesmay be made without departing from the spirit or scope of the invention.As the skilled person will readily appreciate, these figures are merelyof an illustrative nature and are provided only to facilitate theexplanation of various process steps. Accordingly, the relation betweenvarious feature sizes may not necessarily reflect the real situation. Inaddition, in reality, boundaries between specific portions of the deviceand between various layers may not be as sharp and precise asillustrated in these figures.

[0019] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposedsemiconductor surface. Structure must be understood to include silicon,silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium-arsenide. When reference ismade to substrate in the following description, previous process stepsmay have been utilized to form regions or junctions in or on the basesemiconductor or foundation.

[0020] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 3 through 7 illustrate an exemplaryembodiment of a method of fabricating a non-volatile electron storagememory device including an electron trapping layer comprising noblemetal nano-crystals and the resulting device (FIG. 7). FIG. 3 depicts asubstrate fragment of an electron storage device, generally indicatedwith reference numeral 100, shown at a step prior to patterning a gatestructure. The device 100 includes a p-type silicon substrate 3 (forforming an n-channel storage device). Alternatively, an SOI(silicon-on-insulator) substrate may be used in place of the siliconsubstrate 3. A device region is formed on the silicon substrate 21 byconventional process steps. A tunnel oxide layer 22 (first gateinsulating layer) is formed over the silicon substrate 21. The tunneloxide layer 22 may be formed of any suitable insulating material and ispreferably formed of silicon dioxide, a high constant dielectric, or astack of layers including at least one barrier layer and at least onehigh constant dielectric layer. If a high constant dielectric layer isused, preferably a barrier layer (not shown) is formed between the highconstant dielectric layer and the silicon substrate 3. The thickness ofthe tunnel oxide layer 22 depends upon the material selected andprogramming voltages used. For example, a tunnel oxide layer formed ofsilicon dioxide would preferably have a thickness of less than 2 nm.

[0021] Noble metal nano-crystals, preferably platinum (Pt),nano-crystals 23 and preferably having a size of less than about 5 nmthick, are provide over the tunnel oxide layer 22 by chemical vapordeposition (CVD). Platinum nano-crystals may also be deposited viaatomic layer deposition (ALD) and physical vapor deposition (PVD) knownin the art. Platinum nano-crystals are preferably deposited using achemical vapor deposition process wherein, for example,(trimethyl)-methylcyclopentadienyl platinum (IV) is reacted withoxidizing gases such as O₂ and N₂O at about 380-420° C. to depositplatinum on the tunnel oxide layer 22 which self-forms as nano-crystals23 on the tunnel oxide layer 22. In addition to the deposition process,the substrate may be annealed at a temperature of from about 200° C. toabout 800° C., preferably in the presence of N₂ or O₂ in a vacuumatmosphere, to convert the platinum to small nano-crystaltine beads.Furthermore, the nano-crystals 23 may be composed of materials such asRhodium (Rh) and Ruthenium (Ru), which upon oxidation to RuO₂ staysconductive utilizing the aforementioned processing steps. Thenano-crystals 23 are used to shift the threshold voltage of the deviceby trapping electrons in the quantum wells created by the nano-crystals23.

[0022] A gate oxide layer 24 (second gate insulating layer) is formedover the noble metal nano-crystals 23 by CVD. The nano-crystals 23 areformed to be separate and isolated crystals, thus the gate oxide layer24 is formed interstitially between the nano-crystals 23. The gate oxidelayer 24 preferably comprises an advanced dielectric, for example,Ta₂O₅, BaSrTiO₃, HfO₂, or ZrO₂, which have very high dielectricconstants (about 25 or greater) when deposited. Advanced dielectricmaterials are useful for increasing the amount of energy at a givenvoltage that each device can store, thereby reducing operating voltages.As defined herein, an advanced dielectric is a dielectric which allowsdevice scaling below 0.1 μm. Ideally, the noble metal nano-crystals 23are non-reactive and do not oxidize to form a dielectric which coulddestabilize the memory structure as is the case with the prior art. Thefirst and second gate insulating layer 22, 24, together along with thenoble metal nano-crystals 23, comprise a composite dielectric layer.Although not shown, a barrier layer or silicon dioxide layer ispreferably formed over the gate oxide layer 24 when the gate oxide layercomprises an advanced dielectric. A polysilicon gate layer 25 isdeposited on the gate oxide layer 24, preferably by LPCVD, and aninsulating layer 26 formed of silicon nitride is deposited on the gatelayer 25. The polysilicon gate layer 25 may comprise combinations ofpolysilicon, tungsten, tungsten-nitride, polysilicon/tungsten-silicide,polysilicon/tungsten-silicide/tungsten, andpolysilicon/tungsten-nitride/tungsten.

[0023] Referring now to FIG. 4, the layers 22, 23, 24, 25, and 26 arethen etch patterned into a gate stack 20.

[0024] Referring now to FIG. 5, after the gate stack 20 is formed aself-aligned LDD (lightly doped drain) implant (indicated by arrows) isperformed on one or both sides of the gate stack 20 using the gate stack20 as a mask to form LDD regions 26 and 27. FIG. 5 shows the situationwhere LDD implants are provided on both sides of gate stack 20.

[0025] Referring now to FIG. 6 an insulating layer is blanket depositedover the gate stack 20 and etched back to form side wall spacers 28. Thesidewall spacers 28 are preferably formed of a nitride compound, forexample, (Si₃N₄). Nitride compounds are characterized by having etchstopping capabilities. The insulating layer that forms sidewall spacers28 may be deposited by conventional techniques, for example, LPCVD andPECVD. Other preferred examples of an insulating layer material for thesidewall spacers 28 is SiO₂.

[0026] Referring now to FIG. 7, using the sidewall spacers 28 and thegate structure 20 as a mask, an n-type impurity is implanted into asurface of the substrate by ion implantation to form source and drainregions 36 and 37, which include LDD regions 26 and 27. The LDD implantmay be angled. Also, a punch-through p-type implant may be performed.Subsequent conventional process steps are then used to connect the FIG.7 transistor device to other fabricated structures.

[0027] The electron storage device 100 is efficiently fabricated anduses the noble metal nano-crystals 23 as the electron trapping layer.The formation of the nano-crystals 23 is more accurately controlled inthe invention and the use of noble metal nano-crystals 23 allows fordevice integration with advanced high constant dielectrics such asTa₂O₅, Ba SrTiO₃, HfO₂, and ZrO₂, resulting in thinner effective oxides.The use of these advanced dielectrics further allows reduction ofoperating voltages. Accordingly, the semiconductor device of theembodiment is suitable as a non-volatile memory and can be easily scaledfor future technologies. The device can be used as an electron storagedevice which stores one electron per nano-crystal, or as a device whichstores more than one electron per nano-crystal. Furthermore, a deviceaccording to the invention is more reliable in that if one of thenano-crystals fails, the other nano-crystals will not be affected.

[0028] The electron storage device 100 of the invention may be used as anon-volatile memory cell in a non-volatile memory device. FIG. 8illustrates an exemplary processing system 900 which utilizes anon-volatile memory device 101 containing the electron storage device100 of FIG. 7. The processing system 900 includes one or more processors901 coupled to a local bus 904. A memory controller 902 and a primarybus bridge 903 are also coupled the local bus 904. The processing system900 may include multiple memory controllers 902 and/or multiple primarybus bridges 903. The memory controller 902 and the primary bus bridge903 may be integrated as a single device 906.

[0029] The memory controller 902 is also coupled to one or more memorybuses 907. Each memory bus accepts memory components 908, which includeat least one memory device 101 of the invention. Alternatively, in asimplified system, the memory controller 902 may be omitted and thememory components directly coupled to one or more processors 901. Thememory components 908 may be a memory card or a memory module. Thememory components 908 may include one or more additional devices 909.For example, the additional device 909 might be a configuration memory.The memory controller 902 may also be coupled to a cache memory 905. Thecache memory 905 may be the only cache memory in the processing system.Alternatively, other devices, for example, processors 901 may alsoinclude cache memories, which may form a cache hierarchy with cachememory 905. If the processing system 900 include peripherals orcontrollers which are bus masters or which support direct memory access(DMA), the memory controller 902 may implement a cache coherencyprotocol. If the memory controller 902 is coupled to a plurality ofmemory buses 907, each memory bus 907 may be operated in parallel, ordifferent address ranges may be mapped to different memory buses 907.

[0030] The primary bus bridge 903 is coupled to at least one peripheralbus 910. Various devices, such as peripherals or additional bus bridgesmay be coupled to the peripheral bus 910. These devices may include astorage controller 911, an miscellaneous I/O device 914, a secondary busbridge 915, a multimedia processor 918, and an legacy device interface920. The primary bus bridge 903 may also coupled to one or more specialpurpose high speed ports 922. In a personal computer, for example, thespecial purpose port might be the Accelerated Graphics Port (AGP), usedto couple a high performance video card to the processing system 900.

[0031] The storage controller 911 couples one or more storage devices913, via a storage bus 912, to the peripheral bus 910. For example, thestorage controller 911 may be a SCSI controller and storage devices 913may be SCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be an local area network interface, suchas an Ethernet card. The secondary bus bridge may be used to interfaceadditional devices via another bus to the processing system. Forexample, the secondary bus bridge may be an universal serial port (USB)controller used to couple USB devices 917 via to the processing system900. The multimedia processor 918 may be a sound card, a video capturecard, or any other type of media interface, which may also be coupled toone additional devices such as speakers 919. The legacy device interface920 is used to couple legacy devices, for example, older styledkeyboards and mice, to the processing system 900.

[0032] The processing system 900 illustrated in FIG. 8 is only anexemplary processing system with which the invention may be used. WhileFIG. 8 illustrates a processing architecture especially suitable for ageneral purpose computer, such as a personal computer or a workstation,it should be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908 and/or memorydevices 100. These electronic devices may include, but are not limitedto audio/video processors and recorders, gaming consoles, digitaltelevision sets, wired or wireless telephones, navigation devices(including system based on the global positioning system (GPS) and/orinertial navigation), and digital cameras and/or recorders. Themodifications may include, for example, elimination of unnecessarycomponents, addition of specialized devices or circuits, and/orintegration of a plurality of devices.

[0033] The invention is not limited to the details of the illustratedembodiment. Accordingly, the above description and drawings are only tobe considered illustrative of exemplary embodiments which achieve thefeatures and advantages of the invention. Modifications andsubstitutions to specific process conditions and structures can be madewithout departing from the spirit and scope of the invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description and drawings, but is only limited by the scopeof the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A semiconductor device comprising: a gatestructure comprising: a first gate insulating layer formed over asemiconductor substrate; a noble metal nano-crystal electron trappinglayer formed over the first gate insulating layer; a second gateinsulating layer formed over said trapping layer; a gate electrodeformed over the second gate insulating layer; and source and drainregions formed in surface portions of the semiconductor substrate onopposite sides of said gate structure interposed therebetween.
 2. Thesemiconductor device of claim 1 wherein said trapping layer comprisesplatinum.
 3. The semiconductor device of claim 1 wherein said trappinglayer comprises rhodium.
 4. The semiconductor device of claim 1 whereinsaid trapping layer comprises ruthenium.
 5. The semiconductor device ofclaim 1 wherein said second gate insulating layer comprises a highconstant dielectric material.
 6. The semiconductor device of claim 1wherein said second gate insulating layer comprises Ta₂O₅.
 7. Thesemiconductor device of claim 1 wherein said second gate insulatinglayer comprises HfO₂.
 8. The semiconductor device of claim 1 whereinsaid second gate insulating layer comprises ZrO₂
 9. The semiconductordevice of claim 1 wherein said second gate insulating layer comprisesBaSrTiO₃.
 10. The semiconductor device of claim 1 wherein said device isa stored electron device.
 11. The semiconductor device of claim 10wherein said device stores a single electron per nano-crystal.
 12. Thesemiconductor device of claim 10 wherein said device stores more thanone electron per nano-crystal.
 13. The semiconductor device of claim 1wherein said trapping layer is formed by depositing a noble metal oversaid first gate insulating layer via chemical vapor deposition andannealing said trapping layer.
 14. The semiconductor device of claim 1wherein said trapping layer is formed by depositing a noble metal oversaid first gate insulating layer via atomic layer deposition andannealing said trapping layer.
 15. The semiconductor device of claim 1wherein said first gate insulating layer comprises SiO₂.
 16. Thesemiconductor device of claim 1 wherein said first gate insulating layercomprises a high constant dielectric material.
 17. The semiconductordevice of claim 1 wherein said first gate insulating layer comprises astack of layers, said stack of layers comprising at least one barrierlayer formed under a high constant dielectric layer.
 18. Thesemiconductor device of claim 1 wherein said second gate insulatinglayer comprises a stack of layers, said stack of layers comprising atleast one barrier layer formed over an advanced dielectric material. 19.The semiconductor device of claim 1 wherein said second gate insulatinglayer comprises a silicon dioxide layer formed over an advanceddielectric material.
 20. An electron storage device comprising: a gatestructure comprising: a tunneling oxide layer formed over a substrate;an electron trapping layer formed of noble metal nano-crystals providedover said tunneling oxide layer; an insulating layer formed over saidtrapping layer; a gate electrode formed over said insulating layer; andsource and drain regions formed in said substrate on opposite sides ofsaid gate structure.
 21. The device of claim 20 wherein said tunnelingoxide layer comprises a stack of layers, said stack of layers comprisingat least one barrier layer formed under a high constant dielectriclayer.
 22. The device of claim 20 wherein said noble metal is platinum.23. The device of claim 20 wherein said noble metal is rhodium.
 24. Thedevice of claim 20 wherein said noble metal is ruthenium.
 25. The deviceof claim 20 wherein said insulating layer comprises Ta₂O₅.
 26. Thedevice of claim 20 wherein said insulating layer comprises BaSrTiO₃. 27.The device of claim 20 wherein said insulating layer comprises HfO₂. 28.The device of claim 20 wherein said insulating layer comprises ZrO₂. 29.The device of claim 20 wherein said noble metal is formed by annealingsaid electron trapping layer.
 30. The device of claim 20 wherein saidinsulating layer comprises a stack of layers said stack of layerscomprising at least one barrier layer formed over at least one advanceddielectric layer.
 31. The device of claim 20 wherein said insulatinglayer comprises at least one silicon dioxide layer formed over at lestone advanced dielectric layer.
 32. An electron storage devicecomprising: a gate structure comprising: a tunneling oxide layer formedon a substrate; a platinum nano-crystal layer formed over said tunnelingoxide layer; an insulating layer formed over said platinum nano-crystallayer; a gate conductor formed over said insulating layer; and sourceand drain regions provided within said substrate at opposite sides ofsaid gate structure, at least one of said source and drain regions beingan LDD region.
 33. An electron storage device of claim 32 wherein saidinsulating layer comprises Ta₂O₅.
 34. An electron storage device ofclaim 32 wherein said insulating layer comprises BaSrTiO₃.
 35. Anelectron storage device of claim 32 wherein said insulating layercomprises HfO₂.
 36. An electron storage device of claim 32 wherein saidinsulating layer comprises ZrO₃.
 37. The semiconductor device of claim32 wherein said tunneling oxide layer comprises a high constantdielectric material.
 38. The semiconductor device of claim 37 whereinsaid tunneling oxide layer further comprises a barrier layer formedunder said high constant dielectric material.
 39. The semiconductordevice of claim 32 wherein said insulating layer comprises a stack oflayers, said stack of layers comprising at least one barrier layerformed over at least one advanced dielectric layer.
 40. Thesemiconductor device of claim 32 wherein said insulating layer comprisesa stack of layers, said stack of layers comprising at least one silicondioxide layer formed over at least one advanced dielectric layer.
 41. Anelectron storage device comprising: a semiconductor substrate; a gatestructure formed over said substrate; said gate structure comprising: atunneling oxide layer provided over said substrate; a layer of platinumnano-crystals provided over said tunneling oxide layer; a gate oxidelayer provided over said layer of platinum nano-crystals; a conductivecontrol gate provided over said gate oxide layer; and source and drainregions provided on opposite sides of said gate structure.
 42. Anelectron storage device as in claim 41 wherein said source and drainregions are angled lightly doped implants.
 43. An electron storagedevice as in claim 41 wherein said gate oxide layer comprises Ta₂O₅. 44.An electron storage device as in claim 41 wherein said gate oxide layercomprises BaSrTiO₃.
 45. An electron storage device as in claim 41wherein said gate oxide layer comprises HfO₂.
 46. An electron storagedevice as in claim 41 wherein said gate oxide layer comaprises ZrO₂. 47.A processor system comprising: a processor; and a memory device coupledto said processor, said memory device comprising at least on e electronstorage device, said electron storage device comprising: a gatestructure comprising: a first gate insulating layer formed over asemiconductor substrate; a self-formed noble metal nano-crystal electrontrapping layer formed over the first gate insulating layer; a secondgate insulating layer formed over said trapping layer; a gate electrodeformed over the second gate insulating layer; and source and drainregions formed in surface portions of the semiconductor substrate onopposite sides of said gate structure interposed therebetween.
 48. Thesystem of claim 47 wherein said trapping layer comprises platinum. 49.The system of claim 47 wherein said trapping layer comprises rhodium.50. The system of claim 47 wherein said trapping layer comprisesruthenium.
 51. The system of claim 47 wherein said second gateinsulating layer comprises Ta₂O₅.
 52. The system of claim 47 whereinsaid second gate insulating layer comprises BaSrTiO₃.
 53. The system ofclaim 47 wherein said second gate insulating layer comprises HfO₂. 54.The system of claim 47 wherein said second gate insulating layercomprises ZrO₂.
 55. The semiconductor device of claim 47 wherein saidfirst gate insulating layer comprises SiO₂.
 56. The semiconductor deviceof claim 47 wherein said first gate insulating layer comprises a stackof layers, said stack of layers comprising at least one barrier layerformed under said high constant dielectric material.
 57. Thesemiconductor device of claim 47 wherein said second gate insulatinglayer comprises a silicon dioxide layer formed over an advanceddielectric layer.
 58. The semiconductor device of claim 47 wherein saidsecond gate insulating layer comprises at least one barrier layer formedover at least one advanced dielectric layer.
 59. A processor systemcomprising: a processor; and a memory device coupled to said processor,said memory device comprising at least one electron storage device, saidelectron storage device comprising: a gate structure comprising: atunneling oxide layer formed over a substrate; an electron trappinglayer formed of noble metal nano-crystals provided over said tunnelingoxide layer; an insulating layer formed over said trapping layer; a gateelectrode formed over said second insulating layer; and source and drainregions formed in said substrate on opposite sides of said gatestructure.
 60. The system of claim 59 wherein said noble metal isplatinum.
 61. The system of claim 59 wherein said noble metal isrhodium.
 62. The system of claim 59 wherein said tunneling oxide layercomprises a barrier layer formed under a high constant dielectricmaterial.
 63. The system of claim 59 wherein said insulating layercomprises a barrier layer formed over an advanced dielectric material.64. The system of claim 59 wherein said insulating layer comprises asilicon dioxide layer formed over an advanced dielectric material. 65.The system of claim 59 wherein said noble metal is ruthenium.
 66. Thesystem of claim 59 wherein said insulating layer comprises Ta₂O₅. 67.The system of claim 59 wherein said insulating layer comprises BaSrTiO₃.68. The system of claim 59 wherein said insulating layer comprises HfO₂.69. The system of claim 59 wherein said insulating layer is ZrO₂.
 70. Aprocessor system comprising: a processor; and a memory device coupled tosaid processor, said memory device comprising at least one electronstorage device, said electron storage device comprising: a gatestructure comprising: a tunneling oxide layer formed over a substrate; aplatinum nano-crystal layer formed over said tunneling oxide layer; aninsulating layer formed over the platinum nano-crystal layer; a gateconductor formed over said insulating layer; and source and drainregions provided within said substrate at opposite sides of said gatestructure, at least one of said source and drain regions being an LDDregion.
 71. The system of claim 70 wherein said insulating layercomprises Ta₂O₅.
 72. The system of claim 70 wherein said insulatinglayer comprises BaSrTiO₃.
 73. The system of claim 70 wherein saidinsulating layer comprises HfO₃.
 74. The system of claim 70 wherein saidinsulating layer comprises ZrO₃.
 75. A method of manufacturing anelectron storage device comprising the acts of: forming a gate structurecomprising: forming a first gate insulating layer on a semiconductorsubstrate; forming a noble metal electron trapping layer on the firstgate insulating layer containing nano-crystals; forming a second gateinsulating layer on said trapping layer; forming a gate electrode on thesecond gate insulating layer; and forming source and drain regions inthe semiconductor substrate on opposite sides of said gate structure.76. The method of claim 75 wherein said act of forming said noble metalelectron trapping layer comprises annealing said noble metal to formbeads of noble metal nano-crystals.
 77. The method of claim 76 whereinsaid annealing is at a temperature of between about 200° C. and about800° C.
 78. The method of claim 76 wherein said annealing is in anatmosphere comprising O₂.
 79. The method of claim 76 wherein saidannealing is in an atmosphere comprising N₂.
 80. The method of claim 75wherein said noble metal is platinum.
 81. The method of claim 75 whereinsaid noble metal is rhodium.
 82. The method of claim 75 wherein saidnoble metal is ruthenium.
 83. The method of claim 75 wherein said secondgate insulating layer is formed of Ta₂O₅.
 84. The method of claim 75wherein said second gate insulating layer is formed of BaSrTiO₃.
 85. Themethod of claim 75 wherein said second gate insulating layer is formedof HfO₅.
 86. The method of claim 75 wherein said second gate insulatinglayer is formed of ZrO₂.
 87. The method of claim 75 wherein forming saidfirst gate insulating layer comprises forming a stack of layers, saidstack of layers comprising at least one barrier layer formed under atleast one high constant dielectric layer.
 88. The method of claim 75wherein forming said second gate insulating layer comprises forming abarrier layer over an advanced dielectric layer.
 89. The method of claim75 wherein forming said second gate insulating layer comprises forming asilicon dioxide layer over an advanced dielectric layer.
 90. The methodof claim 76 wherein said device stores a single electron pernano-crystal.
 91. The method of claim 76 wherein said device stores morethan one electron per nano-crystal.
 92. The method of claim 75 whereinsaid noble metal is formed by chemical vapor deposition.
 93. The methodof claim 92 wherein said deposition is performed at about 380-420° C.94. The method of claim 92 wherein said deposition is performed byreacting (trimethyl)-methylcyclopentadienyl platinum (IV) with oxidizinggases.
 95. The method of claim 75 wherein said noble metal is formed byatomic layer deposition.
 96. A method of manufacturing an electronstorage device comprising the acts of: forming a gate structurecomprising: forming a tunneling oxide layer over a substrate; forming anoble metal nano-crystal electron trapping layer over said tunnelingoxide layer; forming an insulating layer over said trapping layer;forming a gate electrode over the insulating layer; and forming sourceand drain regions in said substrate on opposite sides of said gatestructure.
 97. The method of claim 96 wherein said act of forming saidnoble metal nano-crystal electron trapping layer comprises annealingsaid noble metal.
 98. The method of claim 97 wherein said annealing isat a temperature of between about 200° C. and about 800° C.
 99. Themethod of claim 97 wherein said annealing is in an atmosphere comprisingO₂.
 100. The method of claim 97 wherein said annealing is in anatmosphere comprising N₂.
 101. The method of claim 96 wherein said noblemetal is formed of platinum.
 102. The method of claim 96 wherein saidnoble metal is formed of rhodium.
 103. The method of claim 96 whereinsaid noble metal is formed of ruthenium.
 104. The method of claim 96wherein said second gate insulating layer is formed of Ta₂O₅.
 105. Themethod of claim 96 wherein said second gate insulating layer is formedof BaSrTiO₃.
 106. The method of claim 96 wherein said second gateinsulating layer is formed of HfO₂.
 107. The method of claim 96 whereinsaid second gate insulating layer is formed of ZrO₂.
 108. The method ofclaim 96 wherein said device stores a single electron per nano-crystal.109. The method of claim 96 wherein said device stores more than oneelectron per nano-crystal.
 110. The method of claim 96 wherein formingsaid tunneling oxide layer comprises forming a layer comprising a highconstant dielectric material and forming a barrier layer over said highconstant dielectric material.
 111. The method of claim 96 wherein saidforming said insulating layer comprises forming a barrier layer over anadvanced dielectric layer.
 112. A method of manufacturing an electronstorage device comprising the acts of: forming a gate structurecomprising: forming a tunneling oxide layer over a substrate; forming aplatinum nano-crystal layer over said tunneling oxide layer; forming aninsulating layer over said platinum nano-crystal layer; forming a gateelectrode over said insulating layer; and forming source and drainregions in said substrate on opposite sides of said gate structure. 113.The method of claim 112 wherein said insulating layer is formed ofTa₂O₅.
 114. The method of claim 112 wherein said insulating layer isformed of BaSrTiO₃.
 115. The method of claim 112 wherein said insulatinglayer is formed of HfO₂.
 116. The method of claim 112 wherein saidinsulating layer is formed of ZrO₂.
 117. A method of manufacturing anelectron storage device comprising the acts of. forming a gate structurecomprising: forming a first gate insulating layer on a semiconductorsubstrate; depositing a nano-crystal layer formed of a noble metal onthe first gate insulating layer; annealing said nano-crystals to formnano-crystalline beads; forming a second gate insulating layer over saidnano-crystals; forming a gate electrode on the second gate insulatinglayer; and forming source and drain regions in the semiconductorsubstrate on opposite sides of said gate structure.
 118. The method ofclaim 117 wherein said annealing is performed at a temperature ofbetween about 200° C. and about 800° C.
 119. The method of claim 117wherein said annealing is performed in an atmosphere comprising O₂. 120.The method of claim 117 wherein said annealing is performed in anatmosphere comprising N₂.
 121. The method of claim 117 wherein saidnano-crystal layer is formed of platinum.
 122. The method of claim 117wherein said nano-crystal layer is formed of rhodium.
 123. The method ofclaim 117 wherein said nano-crystal layer is formed of ruthenium. 124.The method of claim 117 wherein said second gate insulating layer isformed of Ta₂O₅.
 125. The method of claim 117 wherein said second gateinsulating layer is formed of BaSrTiO₃.
 126. The method of claim 117wherein said second gate insulating layer is formed of HfO₂.
 127. Themethod of claim 117 wherein said second gate insulating layer is formedof ZrO₂.
 128. The method of claim 117 wherein said first gate insulatinglayer comprises a high constant dielectric material.
 129. The method ofclaim 128 wherein said first gate insulating layer comprises a silicondioxide layer formed over said high constant dielectric material. 130.The method of claim 117 wherein said first gate insulating layer isformed of a stack of layers, said stack of layers comprising at leastone barrier layer formed under at least one high constant dielectriclayer.
 131. The method of claim 117 wherein said device stores a singleelectron per nano-crystalline bead.
 132. The method of claim 117 whereinsaid device stores more than one electron per nano-crystalline bead.133. The method of claim 117 wherein said nano-cyrstal layer isdeposited by chemical vapor deposition.
 134. The method of claim 133wherein said deposition is performed at about 380-420° C.
 135. Themethod of claim 133 wherein said deposition is performed by reacting(trimethyl)-methylcyclopentadienyl platinum (IV) with oxidizing gases.136. The method of claim 117 wherein said nano-crystal layer isdeposited by atomic layer deposition.